Design Verification Engineer

Description:

• Be involved with the delivery of standard compliant IP blocks and/or Sub Systems for use with OTN/Ethernet/CXL/PCIe ASIC's
• Testbench Development: Design and implement advanced verification environments, including testbenches, test cases, and coverage models, to thoroughly verify IP designs and meet customer specifications.
• Simulation and Debugging: Conduct simulation runs, analyze results, and debug issues to ensure the accuracy and completeness of IP designs, addressing customer feedback and concerns in a timely manner.
• Technical Expertise: Utilize your extensive knowledge and experience in verification methodologies, such as UVM, to offer valuable insights and recommendations to customers, ensuring high-quality verification results.
• Documentation and Training: Develop comprehensive technical documentation, including test plans, reports, and user guides
  

Top Skills/Experience Required:

• 5+ years of Design Verification experience with UVM and SystemVerilog
• Experience with either PCIe OR Ethernet IP
• Experience with Subsystem Level Verification
  

Additional Skills & Qualifications:

• Experience with data link or transaction layer functionalities
• Telecom industry experience
• Experience with Gate Level Simulation
• Experience with Formal Verification
  

WHY ACTALENT?

• Work with a dedicated career partner specialized in your skill set
• We advocate on your behalf so you get what you want and need out of your job
• Get performance feedback, career advice, and access to ongoing professional development tools
• Build your career and learn new skills through projects as diverse as your curiosity
• You are eligible for benefits, paid time off, and competitive wages that are paid weekly